Implementation and Optimization of CNTFET Based Ultra-Low Energy Delay Flip Flop Designs

Energy conservation and delay minimization are the two major goals while designing ultra-low-power digital integrated circuits at lower technology nodes. Here, silicon based carbon nanotube field effect transistor (CNTFET) has been explored as a novel material for future electronics design applications (EDA). In this paper, energy-efficient switching activity techniques have applied with proposed designs. First technique detects completion of sensing stage operation known transition detection (TCD) technique. TC signal generated from NAND complementary outputs which minimizes glitches in latch stage. Another clock gating mechanism to smoothen output waveforms Q \(\overline {Q}\). The existing designs simulated using 32nm CMOS CNTFET technology, indicating that reduces power by 45% 36% respectively comparison conventional CMOS. Proposed Low Power Sense Amplifier Flip Flop control (TCD-LPSAFF) Ultra (ULESAFF) give minimal product (PDP) is 35.7 × 10− 18 J 29.6 respectively. Also, process variation analyzed specified corners (FF, TT SS) temperature range -40∘C 120 ∘C. performance all validated functionality testing load cpacitance, diameter, number tubes pitch